1. Field of the Invention
The present invention relates to a microprocessor, a coprocessor and a data processing system using them, which has a high-speed coprocessor interface, transfers a command to a coprocessor on a small number of us cycles, and can execute a coprocessor instruction at a high speed, and further relates to a microprocessor, a coprocessor and a data processing system using them, which, when an exception has occurred in executing a main processor instruction, can identity a program counter (PC) value of the coprocessor instruction having caused the exception.
2. Description of Related Art
In the data processing system using the conventional microprocessor as a main processing unit (hereinafter referred to as MPU), a configuration is generally adopted that the MPU performs integer operation and a special-purpose coprocessor performs floating-point operation, for example, "Separate-Volume Interface, Numerical Operation Processor, CQ Publication, 1987" describes a data processing system using a microprocessor as a main processor and various floating-point processors as coprocessors.
In such a conventional data processing system, various devices are applied so that the main processor and the coprocessors take share in executing an instruction. FIG. 1 shows a configuration example of a data processing system using the conventional microprocessor and coprocessor.
An MPU 201 controlling the whole of the data processing system, an FPU (Floating-Point Processing Unit) 202 being a coprocessor, a memory system 203 storing instructions and data and a clock generator 204 supplying a clock CLK to the whole of the data processing system are connected by control signal lines 211, 212, 213, 214, 215, 216 and the like. In addition, a signal line 210 transfers the clock CLK, the signal line 211 transfers signals BS#, AS#, DS# and R/W#, the signal line 212 transfers a signal CPST0:2, the signal line 213 transfers a signal CPDC# and the signal line 214 transfers a signal DC# respectively, and the signal line 215 is used as an address bus A0:31 and the signal line 216 is used as a data bus D0:31, respectively.
FIG. 2 is a timing chart when a command, an operand and a PC value of a coprocessor instruction are transferred from the MPU 201 to the FPU 202 in executing the coprocessor instruction in the above-described data processing system as shown in FIG. 1.
In this conventional data processing system, the MPU 201 fetches and decodes a coprocessor instruction, and according to the decoded result, all of the command, the operand, and the PC value of the coprocessor instruction are transferred through the data bus 216.
In the example as shown in the timing chart of FIG. 2, a total of four memory cycles, one memory cycle for command transfer, two memory cycles, one memory cycle at each of high order and low order of data) for operand transfer and one memory cycle for PC value transfer, are needed. An approach for transferring such a command, operand and PC value of the coprocessor instruction with described in detail in "MC 68881/MC 68882 Floating-Point Co-Processor User's Manual", MOTOROLA, INC., PRENTICE HALL, 1987, section 7", or "Separate-Volume Interface, Numerical Operation Processor, CQ Publication, 1987, pp. 194-210".
Also, a data processing system has been proposed so for which adopts an approach that a coprocessor directly fetches a coprocessor instruction, decodes and executes it in place of the method wherein the MPU fetches and decodes a coprocessor instruction and transfers a command to the coprocessor.
For example, in the data processing system using the microprocessor i8086 made by Intel Co. as the MPU, the i8087 being the coprocessor monitors the bus always, and when a coprocessor instruction is outputted to the bus, the coprocessor fetches, decodes and executes this instruction. An approach is described in detail, for example, in "Separate-Volume Interface, Numerical Operation Processor, CQ Publication, 1987, pp. 60-74".
In the data processing system using the conventional microprocessor as the MPU, and using the coprocessor, as shown in the timing chart of FIG. 2, when the MPU directs the coprocessor to make an operation for a coprocessor instruction, it transfers the PC value of the coprocessor instruction together, and therefore a large number of memory cycles are required for directing the operation, and thereby the whole performance is deteriorated. The PC value of the coprocessor instruction is not required directly for executing the coprocessor instruction, but it is transferred to make provision against the case where an exception is generated in executing the coprocessor instruction, and is scarcely utilized, being wasteful.
Also, in the data processing system using the conventional microprocessor as the MPU wherein the coprocessor directly fetches and decodes the coprocessor instruction, an instruction prefetch queue and an instruction decoder like the MPU are required to be provided in the coprocessor, and thereby the quantity of hardware of the coprocessor is increased. Also, in the case where the same coprocessors are connected in a plural number and are operated in parallel, arbitration among the coprocessors becomes necessary for controlling that which coprocessor is to execute which coprocessor instruction. The problems of the data processing system adopting such an approach are described in detail in "Yoshiyuki FURUSAWA, Coming of Large-Scaled Propagation Period of Floating-Point Operation Coprocessor Triggered by the Opening of the Age of 32 Bits, Nikkei Electronics, No. 425, Jul. 13, 1987, pp. 123-138".